Analog Design Issues in Digital VLSI Circuits and Systems: A by Juan J. Becerra, Eby G. Friedman

By Juan J. Becerra, Eby G. Friedman

Analog layout concerns in electronic VLSI Circuits and Systems brings jointly in a single position vital contributions and updated study leads to this fast paced region.
Analog layout concerns in electronic VLSI Circuits and Systems serves as an outstanding reference, supplying perception into one of the most hard examine concerns within the box.

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Extra info for Analog Design Issues in Digital VLSI Circuits and Systems: A Special Issue of Analog Integrated Circuits and Signal Processing, An International Journal Volume 14, Nos. 1/2 (1997)

Example text

Lpeak is the maximum saturation current of the load transistor and depends on both VGs and Vvs. therefore Ipeak is both input waveform and load dependent. tbase 33 is the time during which both the P-channel and the N-channel transistors are turned on, permitting a DC current path to exist between Vvv and ground. This time occurs over the region, VrN ~ V;n ~ Vvv + VTP. Therefore, tbase is found from the difference between (7) and (8), IUvTP - tvTN)I. The area defined by this triangle is ~Ipeak x tbaseo which models the total shortcircuit current lsc sourced by a CMOS inverter due to a non-step input [11].

If the starting point x<0 > of the iteration process is far from the solution x* convergence problems may occur. Calculating the simple one dimensional example given in Figure II demonstrates this occurance. The solid curve in Figure 12 shows the number of Newton-Raphson iterations. Three significant regions can be made out. 67SV. The number of iterations is nearly constant and at 90 too high for the practical use in a simulator. Around the solution the solving procedure is sufficiently fast, but when v<0> » v*, the computational effort increases linearly.

The analytical expression shown in (4) closely approximates SPICE for most of the region of operation for a wide range of load impedances from 10 Q to 1000 Q and from 10 fF to 1 pF. The maximum error of the output response derived from (4) as compared with SPICE (shown in Figure 3) is 25% for the specific case where the RC load is lO Q and lO fF, approaching the unloaded case. B. Analytical Delay Expressions From (4), the propagation delay of a CMOS inverter calculated at the 50% point tpn is + UdaRC (5) 'Udo The transition time of a CMOS inverter driving a lumped RC load calculated at the 90% point t1 is ft C.

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